1. Field of the Invention
The present invention relates to a TDMA (Time Division Multiple Access) mobile telephone apparatus and, more particularly, to a TDMA mobile telephone apparatus designed to shorten the processing time required for a delay equalizer.
2. Description of the Prior Art
Of the conventional TDMA mobile telephone apparatuses, a mobile telephone apparatus using a delay equalizer is designed to receive data including a plurality of slots, which are consecutively transmitted, upon performing slot synchronization with a reception window for capturing only self-slots so as to acquire necessary data. Of the data, only necessary data is equalized by the delay equalizer. The resultant data is then sent as a digital value to a control circuit, a speech conversion circuit, or the like.
FIG. 1 is a block diagram showing a schematic arrangement of a mobile telephone apparatus using a delay equalizer. A radio circuit 20 receives and transmits electric waves. Received data is stored in a data capture circuit 21. When capture of data is completed by the data capture circuit 21, the captured data is supplied to a delay equalizer 22. In the delay equalizer 22, the data is equalized into digital data to be supplied to a control circuit 23 or a speech conversion circuit 24. The speech conversion circuit 24 converts data into speech and causes a speaker section 26 to output it. Control data or speech data from a microphone section 27 is subjected to data conversion in a transmission control section 25, and the resultant data is transmitted to a base station via the radio circuit 20. BER information is bit error rate information input from a detection circuit (not shown) for detecting a bit error rate to the delay equalizer 22.
FIG. 2 is a block diagram showing the internal circuit arrangement of the data capture circuit 21. The arrangement and operation of the data capture circuit 21 will be described with reference to FIG. 2.
The electric field strength and intermediate frequency of received data input from the radio circuit 20 to an A/D conversion circuit 211 and a phase detection circuit 212 are respectively converted into digital data d1 and d2 in response to a conversion clock signal S1 from a counter circuit 213 (for example, the data d1 and d2 respectively consist of 10 bits and 6 bits, i.e., a total of 16 bits). These digital data d1 and d2 are stored in a storage circuit 214 in accordance with a write signal S from the counter circuit 213. When 380 words (one word consisting of 16 bits) are written, the conversion clock signal S1 and the write signal S are disabled. When a write operation with respect to the storage circuit 214 is completed, the delay equalizer 22 loads received data D1 output from the storage circuit 214, and performs equalization processing. The delay equalizer 22 detects an offset from the position of a SYNC word (to be described letter with reference to FIGS. 3A and 3B), and supplies position information data D2 of the SYNC word to a start pulse generation circuit 215. The start pulse generation circuit 215 adjusts the generation timing of a start pulse P by changing the value of an internal counter in accordance with the position information data D2. When the start pulse P is generated by the start pulse generation circuit 215, the counter circuit 213 generates the conversion clock signal S1 and the write signal S to write the digital data in the storage circuit 214. When 380 words are written, these signals are disabled again. Reference numeral 216 denotes a clock pulse generation circuit 216 for outputting reference clock pulse signals S3 and S4 to the counter circuit 213 and the start pulse generation circuit 215, respectively.
FIGS. 3A and 3B show transmission data formats standardized by the Electrical Industries Association (EIA) in the U.S.A to be used between a mobile telephone apparatus and a base station. The transmission data format shown in FIG. 3A is used for transmission from the mobile telephone apparatus to the base station. The transmission data format shown in FIG. 3B is used transmission in the reverse direction, i.e., from the base station to the mobile telephone apparatus. A width "A" of this data format corresponds to the width of one slot to be captured by the mobile telephone apparatus. Note that the numbers respectively represent the numbers of bits of the respective signals.
FIG. 4 shows the data transmission/reception timings in the mobile telephone apparatus. Data (see the data format shown in FIG. 3B) transmitted from the base station is received as slot 1, 2, or 3 by the motile telephone apparatus at the reception timing shown at an upper portion of FIG. 4. Data is transmitted from the mobile telephone apparatus to the base station at the transmission timing shown at a lower portion of FIG. 4. As is apparent from FIG. 4, transmission data (see the data format shown in FIG. 3A) is transmitted before the reception timing at which the mobile telephone apparatus receives a slot.
As described above, in the conventional data capture method using the delay equalizer, even when slot synchronization is to be established at the beginning of reception, data is captured within a frame of a predetermined capture width determined for each data capturing operation. For this reason, if the capture width is small, no sync signal may be captured, resulting in failure in slot synchronization. In order to prevent this, in the conventional method, as indicated by "b" in FIG. 4, the actual capture width is set to be large in advance so as to capture data in a range wider than a range "a", in which data should be captured, by several bits to several tens of bits. With this setting, a sync signal can be reliably captured. That is, the actual capture range includes a data portion (e.g., "RSVD") one data portion before the slot to be received, the slot to be received, and a data portion (e.g., "SYNC") of the next slot. Note that a slot is discriminated by using the SYNC signal.
Once slot synchronization is established, however, unnecessary data is also captured because a reception window is set to be larger than the width of a slot to be received. For this reason, the amount of data processed by the delay equalizer increases. The delay equalizer performs frequency matching, correction of a reception position, and the like in addition to equalization of predetermined data of radio data. Therefore, with an increase in data amount, the processing time required for the delay equalizer prolongs. As a result, the processing may not be performed in time, and transmission/reception may not be smoothly performed.
Furthermore, as the operating time of the delay equalizer prolongs, the power consumption increases.